Systems and methods for identification and elimination of geometrical design rule violations of a mask layout block

ABSTRACT

Computer-implemented systems and methods for eliminating geometrical design rule violations, maintaining mask layout electrical connectivity, reliability verification, and design for manufacturing structural correctness of a mask layout block are provided. Exemplary systems and methods include comparing a feature dimension in a mask layout data file with a design rule in a reference rule file and identifying a design rule violation of a mask layout block if the feature dimension does not match the design rule. Methods may further include automatically correcting the design rule violation by modifying the feature dimension so the feature dimension matches the design rule. A design rule auto-correction tool may be provided and be configured to compare a feature dimension in a mask layout data file with a design rule in a reference rule file and correct the design rule violation. Disclosed embodiments advantageously correct all design rules including dependency rules.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to U.S. patent application Ser. No.63/197,635, filed Jun. 7, 2021, which is hereby incorporated byreference herein in its entirety.

FIELD

The present disclosure relates to systems and methods of eliminatinggeometrical design rule violations and maintaining mask layoutelectrical connectivity, reliability verification, and design formanufacturing structural correctness of a mask layout block.

BACKGROUND

A photomask is an opaque plate with holes or transparencies that allowlight to shine through in a defined pattern. Photomasks are commonlyused in photolithography and in the production of integrated circuits(ICs or “chips”) in particular. Masks are used to produce a pattern on asubstrate, normally a thin slice of silicon known as a wafer in the caseof chip manufacturing. Several masks are used in turn, each onereproducing a layer of the completed design, and together they are knownas a mask set.

A typical semiconductor design process includes numerous steps.Initially, a circuit designer prepares a schematic diagram that includeslogical connections between logic elements that together form anintegrated circuit. The schematic diagram is then tested to verify thatthe logic elements and associated logical connections perform a desiredfunction. Once the circuit is verified, the schematic diagram isconverted into a mask layout database that includes a series ofpolygons. The polygons may represent the logic elements and the logicalconnections contained in the schematic diagram. The mask layout databaseis then converted into multiple photomasks, also known as masks orreticles, that may be used to image different layers of the integratedcircuit on to a semiconductor wafer.

Over the past several years, the number of transistors in asemiconductor device has increased dramatically. Due to this increase,the time to design and manufacture semiconductor devices also hasincreased. As the number of transistors on an integrated circuitcontinues to increase, and the design process for the integrated circuitbecomes more complex, it is more challenging to correct geometricaldesign rules. For example, an increasing number of transistors or aFinFet process may require additional layers and physics-oriented rulesto form the integrated circuit on a semiconductor wafer. Each layerassociated with the integrated circuit may include a complex design rulefor the layer in a desired manufacturing process. The number of designrules for the desired manufacturing process, therefore, significantlyincreases as the number of layers increase and advanced physics-orientedphenomenon formed on the semiconductor wafer.

Typically, the mask layout database is created manually by a layoutdesigner or automatically by a synthesis tool. Once the mask layoutdatabase is complete, spacing between the polygons on the same layer iscompared to the minimum allowable spacing that is included in atechnology file for a desired manufacturing process. This comparison mayidentify design rule violations if the spacing between the polygons orthe dimensions of the polygons in the mask layout database is less thanthe corresponding minimum allowable design rule in the technology file.

Today, any design rule violations in the mask layout database arecorrected manually by a layout designer. The layout designer typicallyfinds each violation and manually corrects the violations by movingpolygons associated with the violations. Especially with advanced chips(14 nm, 10 nm, 7 nm, 5 nm and below . . . ) there are many design rulesthat have dependencies. This is when it becomes a challenge to fixmanually. The layout designer may move a polygon to a specific distance,but he/she has to consider other design rules that may be a dependencyof this violation. Thus, during the correction process, the layoutdesigner may create new design rule violations and, therefore, thecorrection process may need to be repeated until the mask layoutdatabase does not include any design rule violations. The process ofiteratively correcting the design rule violations may take severalhours, days or weeks to complete and can significantly increase the timeneeded to design the integrated circuit.

The additional time required to complete layout may also delay theproduction of a photomask set used to fabricate the integrated circuit.Especially with advanced nanometer processes the process's design rulesare highly complex and depend on electrical and physical phenomena. Amanual correction of these design rules can increase the overallintegrated circuit's design by many months.

Accordingly, there is a need for an automatic system to correct designrules, maintaining the electrical connectivity (LVS) intact. Inaddition, there is a need for new systems and methods to eliminategeometrical design rule violations of a mask layout block and to correctsuch rule violations quickly. There is also a need for systems andmethods of maintaining mask layout electrical connectivity, reliabilityverification, and design for manufacturing structural correctness of amask layout block. There is a need for systems and methods that canconsider and fix all design rule violations, including dependenciesrules that need to be covered.

SUMMARY

The present disclosure, in its many embodiments, alleviates to a greatextent the disadvantages and problems associated with eliminating designrule violations on a photomask. In disclosed embodiments, a photomask isformed by using a mask pattern file created by automatically correctinga design rule violation in a mask layout file. In accordance with anexemplary embodiment, a photomask includes a patterned layer formed onat least a portion of a substrate. The patterned layer may be formedusing a mask pattern file that is created by comparing a featuredimension in a mask layout file with a design rule in a technology file.If the feature dimension is less or greater than the design rule, adesign rule violation is identified and automatically corrected in themask layout file.

In accordance with another exemplary embodiment, an integrated circuitincludes a plurality of interconnect layers, of all types, and aplurality of contact layers that provide electrical connections betweenthe respective interconnect layers. The interconnect and contact layersmay be formed using a plurality of photomasks that are created bycomparing a feature dimension in a mask layout file with a design rulein a technology file. If the feature dimension is less than the designrule, a design rule violation is identified and automatically correctedin the mask layout file. A plurality of mask pattern files thatcorrespond to the interconnect and contact layers are generated from themask layout file.

Important technical advantages of exemplary embodiments include a designrule auto-correction (DRAC) tool that reduces the design time for anintegrated circuit. A design rule check (DRC) tool checks a mask layoutfile for design rule violations and identifies any violations in anoutput file. If the mask layout file contains design rule violations,the DRAC tool reads the coordinates of the violation from the outputfile and automatically adjusts a feature dimension associated with theviolation until the feature dimension is equal, greater, or less thanthe defined design rule for a desired manufacturing process. The timeneeded to verify the mask layout file may be substantially reducedbecause the DRAC tool simultaneously identifies and eliminates thedesign rule violations in the mask layout file.

Another important technical advantage of exemplary embodiments includesa DRAC tool that reduces the size and increases the density of featuresin a mask layout file. In addition to correcting design rule violations,the DRAC tool determines if the spacing between polygons in the masklayout file is greater than the corresponding minimum design rules in atechnology file and reduces the spacing until it is approximately equalto the minimum design rule. The density of the mask layout file,therefore, may be increased, which also increases the number ofintegrated circuits that may be fabricated on a wafer, which is definedas a silicon yield enhancement. The system also provides an Advise Mode.In this mode user can review the found violations individually and/or bycategory and decides if he/she would like to Auto-Correct them or not.

Exemplary systems and methods are based on an artificial intelligenceconvolutional neural network. The convolutional neural network (CNN) isa class of deep neural network, here applied to analyze the mask layoutgraphical data. The CNN reads the mask layout data file in the format ofGDSII, or Oasis (GDS III), CIF or layout editor native data and analyzesall mask layout layers. The system learns the structure and layersdependencies from the design rule deck, then checks the mask layoutdata. The system uses successive approximation heuristics and additionalmethods to significantly shorten the analysis time. This is especiallycrucial with modern integrated circuits that are represented by hugedata.

An exemplary computer-implemented method of eliminating geometricaldesign rule violations of a mask layout block comprises comparing afeature dimension in a mask layout data file with a design rule in areference rule file and identifying a design rule violation of a masklayout block if the feature dimension does not match the design rule.The method may further include automatically correcting the design ruleviolation by modifying the feature dimension so the feature dimensionmatches the design rule. In exemplary embodiments, identifying a designrule violation comprises determining that the feature dimension in themask layout data file is greater or smaller than the design rule in thereference rule file. The design rule may comprise a Voltage-Aware designrule, a DFM-Aware design rule, and/or an RV-Aware design rule.

The step of modifying the feature dimension so the feature dimensionmatches the design rule may comprise adjusting the feature dimensionuntil the feature dimension is exactly equal to the design rule. Thestep of automatically correcting the design rule violation in the masklayout data file may comprise correcting all design rules includingdependency rules. Automatically correcting the design rule violationalso may include repositioning edges of one or more polygons in the masklayout data file until the feature dimension is equal to the designrule. Exemplary methods further comprise presenting the design ruleviolation graphically as one or more violation markers. The design ruleviolation may be a hierarchical design rule violation in a sub-cell ofthe mask layout data file. Exemplary methods further comprise generatinga clean mask layout data file without any design rule violations.

Exemplary embodiments include systems for maintaining mask layoutelectrical connectivity, reliability verification, and design formanufacturing structural correctness of a mask layout block. Suchsystems comprise a design rule auto-correction tool configured tocompare a feature dimension in a mask layout data file with a designrule in a reference rule file. If the feature dimension does not matchthe design rule, the design rule auto-correction tool identifies adesign rule violation and automatically corrects the design ruleviolation by modifying the feature dimension such that the featuredimension matches the design rule.

In exemplary embodiments, the design rule auto-correction tool reducessize and increases density of features in the mask layout data file. Thedesign rule auto-correction tool determines if spacing between polygonsin the mask layout data file is greater than spacing in a minimum designrule and is configured to reduce the spacing between polygons until thespacing is equal to the spacing in the minimum design rule. In exemplaryembodiments, the design rule auto-correction tool considers multiplepatterning and automatically corrects all design rule violations onmultiple layers of an integrated circuit.

The design rule auto-correction tool may include a convolutional neuralnetwork, and the convolutional neural network performs deep learning ofthe mask layout data file. In exemplary embodiments, the convolutionalneural network compares the feature dimension in the mask layout datafile with the design rule in the reference rule file, identifies thedesign rule violation, and automatically corrects the design ruleviolation. Exemplary systems further comprise a violation browserdisplaying the design rule violation.

An exemplary method of analyzing an integrated circuit mask layout datafile and a reference rule file comprises reading a mask layout datafile, reading a reference rule file, comparing a feature dimension inthe mask layout data file with a design rule in the reference rule file,and identifying a design rule violation in the mask layout data file ifthe feature dimension does not match the design rule. Methods mayfurther comprise determining the coordinates of the design ruleviolation in the mask layout data file and automatically correcting thedesign rule violation by modifying the feature dimension so the featuredimension matches the design rule.

Methods may further comprise analyzing interconnecting layers of aplurality of mask layout blocks where the interconnecting layers includea top-level block or cell and one or more sub-blocks or sub-cells. Inexemplary embodiments, identifying a design rule violation in the masklayout data file comprises identifying a design rule violation in one ormore of the top-level cell or the one or more sub-cells andautomatically correcting the design rule violation comprisesautomatically correcting the design rule violation in one or more of thetop-level cell or the one or more sub-cells.

In exemplary embodiments, modifying the feature dimension so the featuredimension matches the design rule comprises adjusting the featuredimension until the feature dimension is greater than or equal to thedesign rule. The reading, comparing, identifying, determining, andautomatically correcting steps may be performed incrementally on masklayout data that has changed since a previous run. Exemplary methodssupport FinFet manufacturing process rules and support digital, analog,analog-mixed signal design, and MEMs mask layout types.

Disclosed embodiments are especially useful with advanced nanometerchips in processes like 7 nm, 5 nm, 3 nm and below, where eachgeometrical design rule has dependencies with other rules. For example,if there is too short a distance between 2 METAL1 layers, and thedesigner is manually moving one METAL 1 polygon farther, it may cause ashort distance to other METAL 1 polygons. Furthermore, this move maytrigger other geometrical design rules violations with other layers.Thus, every manual correction of one or more design rule(s) most likelycauses many other violations. That is why in advanced processes it issuch a time-consuming process. It is a tedious process that typically isdone manually and can take days or weeks. But disclosed embodiments doit in minutes. Given the fact that in an advanced microchip there arebillions of transistors, disclosed embodiments can save 50% or more ofthe global chip's design time.

Accordingly, it is seen that systems and methods of eliminatinggeometrical design rule violations and maintaining mask layoutelectrical connectivity, reliability verification, and design formanufacturing structural correctness of a mask layout block areprovided. These and other features of the disclosed embodiments will beappreciated from review of the following detailed description, alongwith the accompanying figures in which like reference numbers refer tolike parts throughout.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects of the disclosure will be apparent uponconsideration of the following detailed description, taken inconjunction with the accompanying drawings, in which:

FIG. 1A is a process flow diagram showing an exemplary embodiment of amethod of eliminating geometrical design rule violations of a masklayout block in accordance with the present disclosure;

FIG. 1B is a schematic showing an exemplary embodiment of a system ofeliminating geometrical design rule violations of a mask layout block inaccordance with the present disclosure;

FIG. 2A is a schematic showing an exemplary embodiment of a photomaskassembly in accordance with the present disclosure;

FIG. 2B is a schematic showing an exemplary embodiment of a photomaskassembly in accordance with the present disclosure;

FIG. 3 is a cross-sectional view of an exemplary photomask assemblymanufactured in accordance with exemplary methods of the presentdisclosure;

FIG. 4 is a cross-sectional view of an exemplary photomask assemblymanufactured in accordance with exemplary methods of the presentdisclosure and showing a design rule violation;

FIG. 5 is a cross-sectional view of an exemplary photomask assemblymanufactured in accordance with exemplary methods of the presentdisclosure and showing correction of a design rule violation;

FIG. 6 is a layout view of an integrated circuit before an exemplaryembodiment of a design rule auto-correction tool checks featuredimensions in a mask layout file;

FIG. 7 is a layout view of an integrated circuit after an exemplaryembodiment of a design rule auto-correction tool corrects design ruleviolations in a mask layout file;

FIG. 8 is a process flow diagram of an exemplary system for maintainingmask layout electrical connectivity, reliability verification, anddesign for manufacturing structural correctness of a mask layout blockin accordance with the present disclosure;

FIG. 9 is a schematic of an exemplary embodiment of a system formaintaining mask layout electrical connectivity, reliabilityverification, and design for manufacturing structural correctness of amask layout block in accordance with the present disclosure;

FIG. 10 is a process flow diagram of an exemplary design auto-correctiontool in accordance with the present disclosure;

FIG. 11 is a process flow diagram of an exemplary embodiment of a systemfor maintaining mask layout electrical connectivity, reliabilityverification, and design for manufacturing structural correctness of amask layout block in accordance with the present disclosure;

FIG. 12A is a layout view of an integrated circuit before an exemplaryembodiment of a design rule auto-correction tool checks featuredimensions in a mask layout file;

FIG. 12B is a layout view of an integrated circuit after an exemplaryembodiment of a design rule auto-correction tool corrects design ruleviolations in a mask layout file;

FIG. 13 is a schematic of an exemplary embodiment of a system and methodfor maintaining mask layout electrical connectivity, reliabilityverification, and design for manufacturing structural correctness of amask layout block address an aspect of advanced chips calledmulti-patterning;

FIG. 14A is a schematic of exemplary connected mask layout blocksshowing a hierarchical design rule violation in accordance with thepresent disclosure;

FIG. 14B is a schematic of the connected mask layout blocks of FIG. 14Ashowing an exemplary correction of the hierarchical design ruleviolation in accordance with the present disclosure; and

FIG. 14C is a schematic of the connected mask layout blocks of FIG. 14Ashowing an exemplary correction of the hierarchical design ruleviolation in accordance with the present disclosure.

DETAILED DESCRIPTION

In the following paragraphs, embodiments will be described in detail byway of example with reference to the accompanying drawings, which arenot drawn to scale, and the illustrated components are not necessarilydrawn proportionately to one another. Throughout this description, theembodiments and examples shown should be considered as exemplars, ratherthan as limitations of the present disclosure.

As used herein, the “present disclosure” refers to any one of theembodiments described herein, and any equivalents. Furthermore,reference to various aspects of the disclosure throughout this documentdoes not mean that all claimed embodiments or methods must include thereferenced aspects. Reference to materials, configurations, directions,and other parameters should be considered as representative andillustrative of the capabilities of exemplary embodiments, andembodiments can operate with a wide variety of such parameters. Itshould be noted that the figures do not show every piece of equipment,nor the materials, configurations, and directions of the variouscircuits and communications systems.

Exemplary embodiments include systems and methods for automaticelimination of geometrical design rule (DRCs) violations of a masklayout block, maintaining the electrical connectivity (LVS), reliabilityconstraints (RV) and design for manufacturing (DFM) structuralcorrectness. Disclosed embodiments analyze an integrated circuit layoutblock and identify geometrical design rule violations. If a featuredimension does not match a rule deck reference rule disclosed systemsand methods automatically correct the identified design rule violationin the mask layout data. The automatic correction maintains theintegrated circuit mask layout electrical connectivity (LVS),reliability verification (RV) and Design for Manufacturing (DFM)correctness.

Exemplary embodiments modify, move, delete or/and re-create mask layoutpolygons to correct manufacturing process design rule violations. Thesystems and methods work on individual polygons and hierarchicalassembly which includes top level block and sub-blocks. Exemplaryembodiments use artificial intelligence technology in the form ofconvolutional neural networks (CNN) for deep learning of the IC layoutstructure, analysis, and automatic correction. A convolutional neuralnetwork provides the analysis in conjunction with geometrical correctionmethods.

Referring to FIGS. 1A and 1B, an exemplary computer-implemented method 1of eliminating geometrical design rule violations of a mask layout block3 and corresponding system 2 will now be described. An initial step ofthe method 1 is to read 1010 an integrated circuit mask layout databasefile 10. One or more feature dimensions 12, e.g., polygons or othershapes, are analyzed 1030. Exemplary embodiments read 1010 the masklayout database file 10 in GDS II or GDS III (Oasis), or CIF or masklayout editor native environment data file. The method also includesreading 1020 a design rule 14 in a reference rule file 16. Then thefeature dimension 12 in the mask layout database file 10 is compared tothe design rule 14. If there is a photomask design rule violation 18, itis identified 1040 and the coordinates of the design rule violation(s)are determined. A design rule violation 18 would occur if the featuredimension 12 does not match the design rule 14 in the reference rulefile 16. Such a mismatch could arise if the feature dimension 12 in themask layout data file 10 is greater or smaller than the design rule 14.

As best seen in FIG. 1B, various sources serve as inputs to the chipdata for the mask layout block 3. System setups 60 and electrical data62 may be part of the chip data. As discussed above and in more detailherein, the chip data also is comprised of reference rule file 16information and DFM guidelines 55. The chip data for the mask layoutblock 3 communicates certain area restrictions 57, layout parameters 64.In exemplary embodiments, outputs include netlisting 23 and an interface68 to third party tools. As discussed in more detail herein, a recurrentneural network 45 may perform geo analytics 49 as part of the designrule auto-correction 30.

Disclosed methods and systems support any type of design rule. Forexample, Voltage-Aware DRC are supported. Voltage Aware Design Rulesrelate to physical distance, enclosure, or any feature dimension that isdependent on the electric potential difference between the objects(Voltage). In addition, systems and methods support DFM-Aware DRC.Design for Manufacturing aware Design Rules means physical featuredimension between objects that is dependent on DFM rules. RV-Aware DRCare also supported. Reliability Verification aware Design Rules meansphysical feature dimension between objects that is dependent onreliability constraints like Electromigration, Self-Heat, IR Drop andother related rules.

In the event of a design rule violation 18, it may be automaticallycorrected 1080 by modifying the feature dimension 12 so it matches thedesign rule 14. In the case where the feature dimension 12 is greater orsmaller than the design rule 14, the feature dimension 12 would bemodified or adjusted until it is exactly equal to the design rule 14. Inexemplary embodiments, automatically correcting the design ruleviolation 18 comprises repositioning edges 20 of violating polygons 112in the mask layout data file 10 until the feature dimension is equal tothe necessary design rule 14. The method could have an Advise Mode, inwhich the tool highlights the design rule violation 18 withoutcorrecting it, and an Auto-Correction Mode 30.

FIGS. 2A-5 illustrate how a design rule violation 18 could arise and howexemplary methods correct the violation. FIG. 2A shows exemplaryparameters of a photomask assembly 11 such as an enclosure (a) formed bya first polygon 12 within a second polygon 12, a space (b) between twopolygons 12, overlap (c) between two polygons 12, the width (d) of apolygon, and an extension (e) of a polygon 12 beyond another polygon 12.In FIG. 2B, a more complex photomask assembly 11 is shown with severalmetals or polygons 12 enclosing contacts 13 with multiple distances(a)-(n). When any of these distances is greater or less than specifiedin a design rule 14, then a design rule violation 18 occurs.

In the photomask assembly 11 shown in FIGS. 3-5 , a minimum distance Ais necessary to comply with the design rule deck. Distance D is not aviolation since it is greater than distance A, but it is a waste ofsilicon space. To eliminate that waste, as shown in FIG. 4 , a usermoves one of the polygons 112, in an attempt to correct the design ruledistance. Accidently, the user places the polygon 112 too close to theother Metal 1 polygon, creating a design rule violation 18 because thedistance A is less than the minimum allowed by the design rule 14. FIG.5 shows the mask layout after processing by disclosed systems andmethods. The polygon 12 (formerly 112 when it was a violating polygon)is moved to a correct distance according to the design rule deckreference and the violation is fixed.

FIGS. 6 and 7 illustrate another example of a design rule violation 18,i.e., an enclosure type violation. In this example, the Metal 1 Polygon12 is enclosing the contact 13 with an enclosure 15 having less than theminimal enclosure distance 17, thereby creating a design rule violation18 in an integrated circuit. FIG. 7 shows the mask layout afterprocessing by disclosed methods and systems. The Metal 1 Polygon 12 isnow enclosing contact 13 with the correct enclosure distance 17according to the design rule 14 deck file reference.

Exemplary methods include checking and correcting a variety of ruletypes, including but not limited to, geometrical, electrical, andmanufacturing design rules to maintain the mask layout data electricalconnectivity (LVS—Layout vs Schematic) correctness, Design forManufacturing (DFM) rules, and reliability (RV—Reliability verification)correctness. After correcting all design rule violations 18, a cleanmask layout data file without any design rule violations would begenerated 1090. The clean mask layout data file may be generated inGDSII or GDS III (Oasis), CIF or native mask layout editor.

Turning to FIGS. 8-9 , exemplary systems 2 for maintaining mask layoutelectrical connectivity, reliability verification, and design formanufacturing structural correctness of a mask layout block feature adesign rule auto-correction tool 30. The tool 30 reads all layoutpolygons, measures distances, widths, lengths, relative distances,ratios, and inter-layers relations. The design rule auto-correction tool30 compares feature dimensions 12 in a mask layout data file 10 with adesign rule 14 in a reference rule file 16. If a feature dimension 12does not match the design rule 14, the tool identifies a design ruleviolation 18 and automatically corrects the design rule violation byadjusting or modifying the feature dimension 12 so it matches the designrule 14. In exemplary embodiments, the design rule auto-correction tool30 includes an Advise Mode 1050, in which the tool highlights the designrule violation 18 without correcting it.

A design rule violation report serves as an input for the tool 30. Thetool 30 reads the design rule violation report, which could be producedby a third-party tool or be generated by the design rule auto-correctiontool 30. The second input is a process design rule deck file 16, whichincludes a numerical description of all layers, their relations, andtheir design rules. This may be the reference for the automaticcorrection.

Another optional input for the design rule auto-correction tool 30 is anelectrical current analysis data file 19, which typically is generatedby electrical simulation tools and contains information on constraints33, e.g., electrical, RV, DFM. In this node each electrical node currentis defined. This data can be fed into the tool 30 to maintain theelectrical characteristics of the overall circuitries. The tool 30 takesthese current constraints into account to maintain the circuits'behavioral and featured characteristics. A reliability data file can beprovided as another input for the tool 30. In this rule deck file thereare allowable currents for polygons at risk of physical reliability likeelectromigration or self-heat phenomenon. The design ruleauto-correction tool 30 takes this data into account in order tomaintain the overall circuitries' electrical reliability andsustainability.

Based on the design rule violation report and all related rule decksreference mentioned above, the design rule auto-correction tool 30processes the IC layout data, modifying, moving, removing, re-creatingto correct design rule violations, including hierarchical types whichmay occur between sub cells. The system may shift sub-cells, modifytheir polygons, and grow or shrink their size. All these operations canbe done without damaging the electrical connectivity (i.e., maintainingthe wires' connections and hookups), or damaging reliability constraints(i.e., keeping wires' correct width [Compensating if needed], length,number of vias and similar), or damaging design for manufacturingconstraints (DFM, i.e., distances between wires, polygons widths or anyother DFM related design rule). The design rule auto-correction tool 30also may generate an extracted layout netlist 23 and a report 25 onfixing the results. After the system 2 performs the requisite erroranalysis 27, or correction verification, a final clean layout review 29is done and the correct layout is ready 31.

One of the most significant advantages of disclosed embodiments is thatthe automatic corrections of design rule violations 18 in the masklayout data file 10 includes correcting all design rules, includingdependency rules, producing the correct layout 21. With certain advancedchips, many design rules have dependencies. Thus, the correction processitself may create additional violations because correcting a particulardesign rule can create new design rule violations. Advantageously,disclosed systems and methods consider and fix all design rules,including dependencies rules that need to be covered. The capability ofthe systems and methods to see the “global picture” of the entire chip'slayout (which can be very large) and fix all design rules, includingtheir dependencies rules, on the fly is a significant innovation.

Exemplary embodiments perform auto-correction utilizing the rippleeffect, which involves massively moving/editing/shifting/etc. numerouspolygons at the same time and analyzing and fixing on-the-fly the masklayout block's data. Using the ripple effect, the system analyzes themask layout block and takes all polygons' design rules into consideringand solving a giant puzzle. In exemplary embodiments, it starts to workon the left-most corner of the block, moving/shifting/editing polygonsas it progresses with the layout block. It might make a preliminarydecision to start at the left-most corner of a block or it may cut theblock to few virtual sub-blocks and work on all of them in parallel,then assemble them together. The decision where to start the analysismay be made using a successive approximation algorithm.

The ripple effect may be visually accessible to the designer. Afterpressing a “FIX” button, he/she may see rapidly, on screen, manypolygons quickly shifting/moving/modified as the program takes intoconsideration numerous design rules to be obeyed. The user allows (Viasetup GUI) the system to grow the layout block in the X or Y directionsor both. Sometimes, a grow is needed due to lack of space. If the userdoesn't allow automatic growth in any direction the program will flagvisually on screen, using markers areas that were not fixed due to the“not enough room” limitation. The ripple effect may be achieved via arecurrent neural network (RNN) 45 and convolutional neural network (CNN)32, as discussed in more detail herein.

Referring to FIGS. 10 and 11 , the design rule auto-correction tool 30may include a convolutional neural network 32, which incorporates deeplearning methods to perform fast and efficient data processing. Arecurrent neural network 45 also may conduct design rule analysis 47during the analysis phase and a global analysis 49 duringimplementation. Integrated circuit layout data typically is processed insegments, which is done according to a proprietary database splittingprocess. Heuristic processes work with computational geometry methods tocreate a successive approximation of derived layers to speed up thecalculations and take all design rule dependencies into account.Especially with advanced nanometer processes there are thousands ofdesign rule dependencies that need to be satisfied to meet the processmanufacturing requirements. For example, a metal wire must have adifferent length if it runs more than a specific length or have to be ina different width if it has other wires near it.

The convolutional neural network 32 performs deep learning of the masklayout data file 10, analyzing for design rules, finding rules'correlations, and performing auto-correcting operations 35. By this deeplearning, it acquires knowledge 37 about the required feature dimensionsand design rules and develops a knowledge base 39 of this information.In exemplary embodiments, a recurrent neural network 45 is included inthe system to help process knowledge inputs such as data from the masklayout data file 10.

The convolutional neural network 32 performs analysis 41 on theinformation. More particularly, it compares feature dimensions 12 in themask layout data file 10 with design rules 14 in the reference rule file16, identifies any design rule violations 18, and automatically correctsthe design rule violations 18 to maintain electrical connectivity (LVS),reliability (RV) and manufacturing (DFM—Design for Manufacturing) rulescorrectness. The design rule analysis takes into account design rulesfrom the design rule file 16, DFM guidelines 55, and other constraints33. CNN 32 also analyzes certain restrictions 57 and communicates themto RNN 45 for design rule autocorrection. Optimization 59 may beperformed by both the CNN 32 and the RNN 45. Ultimately, the systemgenerates a fixed, correct mask layout 31.

FIGS. 12A and 12B illustrate another example of correcting a photomaskassembly 11 using the auto-correction 35 and optimization 59 describedabove. The distance between polygon 12 a and polygon 12 b is less thanthe minimal distance 17, thereby creating a design rule violation 18 inan integrated circuit. FIG. 12B shows the mask layout after processingby disclosed methods and systems. The polygon 12 a is now located thecorrect distance 17 from polygon 12 b according to the design rule 14deck file reference.

With reference to FIG. 13 , exemplary embodiments address an aspect ofadvanced chips called multi-patterning. This concept introduces anotherhigh complexity challenge to fix geometrical design rules. Generally,multiple-patterning is creating layout polygons on top of each other. InFIG. 13 , the chip's original layout 50 can be seen, as well as doublepatterning 52 and triple patterning 54. Typically, a microchip is builtin multiple layers, isolated by an insulation layer. Using multiplelayers allows manufacturers to add more circuitries on the siliconwafer. The systems and methods disclosed herein take into considerationthe multiple patterning aspect and automatically correct all layoutviolations. In other words, these are multiple-patterning aware designrule auto correction systems.

It should be noted that a design rule typically defines the minimum ormaximum or a geometrical combination allowable dimension for a featurefabricated on a specific layer. For example, an integrated circuit mayinclude, among other layers, a polysilicon layer that forms thetransistor gates, a metal layer that forms interconnects betweentransistors and a contact or via layer that connects the polysiliconlayer to the metal layer. Each layer typically has at least one or moredesign rules associated with features in a mask layout file that areformed on the specific layer. The metal layer may include design rulesfor minimum, maximum or dependent allowable spacing between two or moreadjacent metal features, minimum width of a metal feature and minimumand/or maximum length of a metal feature. The polysilicon and contactlayers may include similar design rules where the minimum or maximumallowable dimensions are unique to that layer.

Thus, a microchip, especially an advanced one, is built with manyhierarchies to make things faster. Typically, a designer starts withbuilding a small block, then places it in another one, adds morecircuits around it and places it into another one, and so forth. Acomplete layout of a full chip can have around 100 levels of hierarchyor more. Each block has to go through the same sets of design rulechecks and other checks. Thus, it is extremely complicated to fixviolations between hierarchies since there may be not enough space, andother considerations.

Turning now to FIGS. 14A-14C, disclosed systems and methodsadvantageously identify and correct hierarchical design rule violationsin these different layers and sub-cells automatically, saving months ofmanual human fixing. An exemplary method performs auto-correction on ahierarchical photo mask layout assembly defined by connected sub-masklayout blocks 3. The steps may include comparing a feature dimension 12in at least one instance of a sub-cell or sub-mask layout block 3 b in amask layout file 10 with a design rule 14 in a reference rule file 16and identifying a hierarchical design rule violation 18 in one or moreinstances of a sub-cell 3 b in the mask layout file 10 if the featuredimension 12 is less or greater than the design rule 14.

A hierarchical design rule violation 18 is a dimension-sized violationwhen two layout blocks 3 a, 3 b are placed near each other. The solutionis a hierarchical geometrical fix. Layout blocks are made individually,cleaned for design rules, and assembled together. Even if the blocksthemselves are DRC clean, i.e., design rule violations=0, just placingthem together can create a situation where some polygons are too closeto others, which then creates a hierarchical DRC violation. An exampleof such a situation is shown in FIG. 14A, where a hierarchical DRCviolation 18 occurs because polygon 12 a of cell or layout block 3 a istoo close to polygon 12 b of sub-cell or layout block 3 b. In otherwords, a hierarchical violation 18 was created by the operation ofputting two base cells together.

In such situations, disclosed systems and methods go into the blocks andshift polygons inside them to eliminate the violation 18. In this firstauto-fix option, illustrated in FIG. 14B, the system stretched thepolygon 12 b away from polygon 12 a, so the two polygons are no longertoo close to each other. This option may be chosen by the system forthis type of fix since it doesn't consume more space and utilizes theexisting space. It should be noted that exemplary systems and methodsautomatically evaluate many options to fix the layout and choose theoptimal solution in order not to grow the layout block or the cell ordamage other of its characteristics like electrical connectivity, DFMand Reliability. In exemplary embodiments, space is the highest priorityin such an evaluation. This is because growing the block means more realestate on the silicon, which would result in fewer chips on the samesilicon. Other considerations relate to the chip's functionality, e.g.,electrical connectivity

If necessary, the system also slightly shifts one or both blocks 3 a, 3b away from each other to eliminate the violation 18. Such a process isvery complex; as blocks grow each one can contain hundreds of millionsof polygons. An example of this second auto-fix option is shown in FIG.14C, where the system shifts the lower block 3 b down and away from theupper block 3 a, creating larger space between polygons 12 a and 12 band eliminating the hierarchical DRC violation 18. This solutionprobably would not be chosen in this instance because it wouldunnecessarily take up extra space on the silicon.

Thus, exemplary embodiments work on interconnecting layers,automatically correcting geometrical design rules of mask layout fileincluding individual polygons, instances of a sub-cells and all othermask layout objects. Then the design rule violation 18 is automaticallycorrected in each instance of the sub-cells, possibly including thetop-level cell or assembly block and the corresponding interconnectlayers. Disclosed systems and methods also offer settings to enable cellor sub-cell growth in the X and/or Y direction in case there is notenough room to correct the design rule violations.

In exemplary embodiments, disclosed systems and methods work in parallelprocessing and may split the processing over numerous CPUs/GPSs over anetwork. This advantageously achieves higher processing speed. Disclosedembodiments also work incrementally, which means processing only thechanged data since the previous run or last set of modifications. Thisfeature saves a significant amount of time.

Exemplary systems and methods can be launched via a graphical userinterface (GUI) 43 and background batch process. Design rule violationscan be presented graphically 1060 as violation markers within the masklayout editor native environment. The system may include a violationbrowser to show each design rule violation, offering the option toautomatically correct each one individually to the correct processdesign rule.

Exemplary embodiments advantageously support FinFet manufacturingprocess geometrical design rules, maintaining electrical, reliabilityand DFM rules correctness. Disclosed embodiments also support Digital,Analog, AMS (Analog-Mixed Signal Design) and MEMs mask layout types. Thesystems and methods can be integrated with existing mask layout,industry standard editors via scripting languages.

Thus, it is seen that systems and methods for eliminating geometricaldesign rule violations of a mask layout block and maintaining masklayout electrical connectivity, reliability verification, and design formanufacturing structural correctness of a mask layout block areprovided. It should be understood that any of the foregoingconfigurations and specialized components or connections may beinterchangeably used with any of the systems of the precedingembodiments. Although illustrative embodiments are describedhereinabove, it will be evident to one skilled in the art that variouschanges and modifications may be made therein without departing from thescope of the disclosure. It is intended in the appended claims to coverall such changes and modifications that fall within the true spirit andscope of the present disclosure.

What is claimed is:
 1. A computer-implemented method of eliminatinggeometrical design rule violations of a mask layout block, comprising:comparing a feature dimension in a mask layout data file with a designrule in a reference rule file; identifying a design rule violation of amask layout block if the feature dimension does not match the designrule; and automatically correcting the design rule violation bymodifying the feature dimension such that the feature dimension matchesthe design rule.
 2. The method of claim 1 wherein identifying a designrule violation comprises determining that the feature dimension in themask layout data file is greater or smaller than the design rule in thereference rule file.
 3. The method of claim 1 wherein modifying thefeature dimension such that the feature dimension matches the designrule comprises adjusting the feature dimension until the featuredimension is exactly equal to the design rule.
 4. The method of claim 1wherein automatically correcting the design rule violation in the masklayout data file comprises correcting all design rules includingdependency rules.
 5. The method of claim 1 wherein the design rulecomprises one or more of: a Voltage-Aware design rule, a DFM-Awaredesign rule, or an RV-Aware design rule.
 6. The method of claim 1further comprising presenting the design rule violation graphically asone or more violation markers.
 7. The method of claim 1 wherein thedesign rule violation is a hierarchical design rule violation in asub-cell of the mask layout data file.
 8. The method of claim 1 furthercomprising generating a clean mask layout data file without any designrule violations.
 9. A system for maintaining mask layout electricalconnectivity, reliability verification, and design for manufacturingstructural correctness of a mask layout block, comprising: a design ruleauto-correction tool configured to compare a feature dimension in a masklayout data file with a design rule in a reference rule file; wherein ifthe feature dimension does not match the design rule, the design ruleauto-correction tool identifies a design rule violation andautomatically corrects the design rule violation by modifying thefeature dimension such that the feature dimension matches the designrule.
 10. The system of claim 9 wherein the design rule auto-correctiontool includes a convolutional neural network.
 11. The system of claim 10wherein the convolutional neural network performs deep learning of themask layout data file.
 12. The system of claim 11 wherein theconvolutional neural network compares the feature dimension in the masklayout data file with the design rule in the reference rule file,identifies the design rule violation, and automatically corrects thedesign rule violation.
 13. The system of claim 9 wherein the design ruleauto-correction tool reduces size and increases density of features inthe mask layout data file.
 14. The system of claim 9 wherein the designrule auto-correction tool determines if spacing between polygons in themask layout data file is greater than spacing in a minimum design ruleand is configured to reduce the spacing between polygons until thespacing is equal to the spacing in the minimum design rule.
 15. Thesystem of claim 9 further comprising a violation browser displaying thedesign rule violation.
 16. The system of claim 9 wherein the design ruleauto-correction tool considers multiple patterning and automaticallycorrects all design rule violations on multiple layers of an integratedcircuit.
 17. A method of analyzing an integrated circuit mask layoutdata file and a reference rule file, comprising: reading a mask layoutdata file; reading a reference rule file; comparing a feature dimensionin the mask layout data file with a design rule in the reference rulefile; identifying a design rule violation in the mask layout data fileif the feature dimension does not match the design rule; determining thecoordinates of the design rule violation in the mask layout data file;and automatically correcting the design rule violation by modifying thefeature dimension such that the feature dimension matches the designrule.
 18. The method of claim 17 wherein modifying the feature dimensionsuch that the feature dimension matches the design rule comprisesadjusting the feature dimension until the feature dimension is greaterthan or equal to the design rule.
 19. The method of claim 17 furthercomprising analyzing interconnecting layers of a plurality of masklayout blocks, the interconnecting layers including a top-level cell andone or more sub-cells.
 20. The method of claim 19 wherein identifying adesign rule violation in the mask layout data file comprises identifyinga design rule violation in one or more of the top-level cell or the oneor more sub-cells and automatically correcting the design rule violationcomprises automatically correcting the design rule violation in one ormore of the top-level cell or the one or more sub-cells.
 21. The methodof claim 17 wherein the reading, comparing, identifying, determining,and automatically correcting steps are performed incrementally on masklayout data that has changed since a previous run.
 22. The method ofclaim 17 supporting FinFet manufacturing process rules and supportingdigital, analog, analog-mixed signal design, and MEMs mask layout types.